The present invention relates to integrated circuits and similar devices generally and to methods for the manufacture thereof.
An essential step in the manufacture of all integrated circuit devices is known as xe2x80x9cpackagingxe2x80x9d and involves mechanical and environmental protection of a silicon chip which is at the heart of the integrated circuit as well as electrical interconnection between predetermined locations on the silicon chip and external electrical terminals.
At present three principal technologies are employed for packaging semiconductors: wire bonding, tape automatic bonding (TAB) and flip chip.
Wire bonding employs heat and ultrasonic energy to weld gold bonding wires between bond pads on the chip and contacts on the package.
Tape automatic bonding (TAB) employs a copper foil tape instead of bonding wire. The copper foil tape is configured for each specific die and package combination and includes a pattern of copper traces suited thereto. The individual leads may be connected individually or as a group to the various bond pads on the chip.
Flip chips are integrated circuit dies which have solder bumps formed on top of the bonding pads, thus allowing the die to be xe2x80x9cflippedxe2x80x9d circuit side down and directly soldered to a substrate. Wire bonds are not required and considerable savings in package spacing may be realized.
The above-described technologies each have certain limitations. Both wire bonding and TAB bonding are prone to bad bond formation and subject the die to relatively high temperatures and mechanical pressures. Both wire bond and TAB technologies are problematic from a package size viewpoint, producing integrated circuit devices having a die-to-package area ratio ranging from about 10% to 60%.
The flip-chip does not provide packaging but rather only interconnection. The interconnection encounters problems of uniformity in the solder bumps as well as in thermal expansion mismatching, which limits the use of available substrates to silicon or materials which have thermal expansion characteristics similar to those of silicon.
The patent literature is extremely rich in the area of integrated circuits and methods for the manufacture thereof.
Described in applicant""s published PCT Application WO 95/19645 are methods and apparatus for producing integrated circuit devices.
The following U.S. Pat. Nos. and patent applications of the present inventor are considered to be particularly relevant: U.S. Pat. Nos. 5,716,759; 5,547,906; 5,455,455 and Ser. No. 08/952,019.
The present invention seeks to provide improved packaged crystalline substrate based devices and methods for producing same.
There is thus provided in accordance with a preferred embodiment of the present invention a crystalline substrate based device including a crystalline substrate having formed thereon a microstructure and at least one packaging layer which is sealed over the microstructure by an adhesive and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer.
There is also provided in accordance with a preferred embodiment of the present invention a chip scale packaged crystalline substrate including:
a substrate having formed thereon a microstructure; and
at least one chip scale package which is sealed over the microstructure and defines therewith at least one gap.
There is additionally provided in accordance with a preferred embodiment of the present invention a method of producing a crystalline substrate based device including:
providing a microstructure on a substrate; and
adhesively sealing at least one packaging layer over the microstructure and at least partially spaced therefrom, thereby to define a gap between the microstructure and the at least one packaging layer.
Preferably, at least one packaging layer is sealed onto the crystalline substrate using an adhesive, such as epoxy.
In accordance with a preferred embodiment of the present invention, the crystalline substrate includes silicon, lithium niobate, lithium tantalate or quartz.
Preferably, the at least one packaging layer is transparent.
The at least one cavity may include a single cavity or a plurality of cavities.
The microstructure may include a micromechanical structure, a microelectronic structure and/or an optoelectronic structure.